Today many electronic devices include a memory device to store data. Generally, in conventional memory devices with a serial protocol interface (SPI), a memory byte address to be accessed is specified by one or more commands. When the bus width is 8 input/output (I/O) bits or more, with a double transfer rate (DTR) or double data rate (DDR) interface, the least significant bit (LSB) A0 of byte address may be unused because the output would be 2 bytes (or 1 word) per clock cycle, i.e., a first byte on a clock rising edge and second byte on a clock falling edge.
FIGS. 1A and 1B are timing diagrams showing waveforms of data output segments of a memory read operation. In FIGS. 1A and 1B, the waveforms include an 8-bit memory address followed by data output DQ[7:0], a clock signal WTG, and a chip select signal CSB. The read operation illustrates a DTR 8 I/O interface, in which one word (or 2 bytes) in each clock cycle is output in two different sequences. First, referring to FIG. 1A, a high byte (or odd byte) is output before a low byte (or even byte). This sequence is called “high-byte-first,” in which odd bytes are output before even bytes. Second, referring to FIG. 1B, a low byte (or even byte) is output before a high byte (or odd byte). This sequence is called “low-byte-first,” in which even bytes are output before odd bytes.
Generally, a memory device utilizes only one of the “high-byte-first” or “low-byte-first” sequences. Memory device vendors therefore need to provide different devices to fulfill the demand for different data input or output sequences.